In this instructable we are gonna design a simple VGA Controller in RTL. VGA Controller is the digital circuit designed to drive VGA displays. It reads from Frame Buffer (VGA Memory) which represents the frame to be displayed, and generates necessary data and sync signals for display purpose.
Following are the main interface signals in a VGA Controller
For the VGA display chosen, you have to first calculate the frequency of Pixel Clock needed to drive it. It depends on 3 parameters: Total Horizontal Pixels, Total Vertical Pixels, Screen Refresh Rate.
Typically, F = THP * TVP * Refresh Rate
Find the documentation on pixel clock needed for various VGA displays, in the attached RAR.
HSYNC and VSYNC signals are generated from Pixel clock. The timing of HSYNC and VSYNC signals depend on number of parameters: Horizontal and Vertical Frontporch, Horizontal and Vertical Backporch, Horizontal and Vertical Display Pixels, Horizontal and Vertical Sync Pulse Widths and Polarities.
These parameters are standardized for a chosen VGA display. Find these documents in the attached RAR.
These parameters are configurable parameters in our VGA Controller IP.
The figure shows how to integrate VGA Controller with a VGA display. You need two more components to complete the system:
One of the simplest and popular Video DACs is ADV7125. It is an 8-bit DAC that converts RGB digital words to 0-0.7 V analog signals and drive the VGA display.
It is the memory that 'stores' the image to be displayed. It is typically a RAM or sometimes ROM. We will discuss how to design a frame buffer to represent an image. Frame buffer passes this digital info to a Video DAC on command from VGA Controller.
First we have to decide the pixel depth needed. It decides the quality of the image, the variety of colors a pixel can represent. For an 8-bit DAC, we need to represent the primary color components of a pixel: R, G, and B in 8 bits each. It means, a pixel is of 24-bit.
Each pixel is stored in a contiguous manner in Frame Buffer memory locations.
Suppose an image to be displayed is 800x600 pixels.
Therefore Frame Buffer needed is 800x600 = 480000 x 24 bits memory
Total size of the memory is 800x600x24 = 1400 kB approx.
If black and white image, 800x600x1 = 60 kB approx.
Block RAMs maybe used to represent a Frame Buffer in Xilinx FPGAs.
The RAR contains: