I do this instructable because it looks like there is not simple getting started tutorial to teach people to use the latest Xilinx Vivado CAD tool. So, I want to use the simple multiple inputs gate design to walk through Xilinx Vivado CAD. I will use Verilog Hardware Design Language to create the logic design. The design will be then implemented in the Digilent Nexys 4 FPGA (Field Programmable Gate Array) development board.
Digital / Logic design is a fundamental but important knowledge. It is the design of circuits and systems that form the base of all electronics. FPGAs are programmable semiconductor devices that are based around a matrix of Configurable Logic Blocks (CLBs) connected through programmable interconnects. If you want to know more about FPGA, you can go to Xilinx or National Instruments website.
Verilog is basedon the C programming language and is the most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. You can find out the details in the Digilent Intro to Verilog Project
Go to Xilinx website http://www.xilinx.com/products/design-tools/vivado/ and then click downloads in the left hand side of the webpage.
Once you finish the download, you can create the free Vivado Webpack license. You can find out the instruction at http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/iil.pdf (page 6-9)
Once you have finished the download and created the free license. Open the Vivado Webpack (If you are window users, you will find the program in the All Programs or desktop.
Click "Create File". Then, there is "Create Source File" pop up. Choose Verilog in file type. Name the file "Circuit1" and choose file location to <location to project>. Click OK --> Next --> Next. Then, you need to choose the part. Digilent Nexys 4 is based on XC7A100T-1CSG324C. So, we should choose family: Artix 7 and package:CG324, speed grade: -3. Highlight the XC7A100T1CSG324-3 (last option) and click Next --> Finish.
First, hide the "Design Run" Panel by clicking the minimizing button
Double click "Circuit1" module to start to write the Verilog program. You will see there are some default syntax.
module Circuit1(
input x,
output z
);
endmodule
Module Circuit1 --> Circuit 1
input x --> the input we created
output --> the output we created
The parenthesis ( ) in the module definition
The semi-colon ";" to run the syntax
We want 4 inputs, so we do an array of 0 to 3. The syntax will be
module Circuit1(
input [3:0] x, // create 4 inputs
output z // create one input
);
endmodule
Then, we also want to assign the AND relationship to the output. So, we write
assign z = &x;
We want to instantiate the module so that the design can be implemented in the FPGA board.
Highlight the Circuit1 module. Click Add Sources
Select Add / Create a Design Source and Click Next
Click "Create File" and then name the file "circuit1_top". Choose the Verilog and . Click OK --> Finish
We want to use switch as inputs and LED as output in the Nexys 4, so we create sw (switches), led (LED) as inputs and output in the circuit1_top module. Click OK.
Double click the circuit1_top module.
Write the following Verilog program
module circuit1_top(
input [3:0} sw, // create 4 inputs
output [0:0]led // create one output
);
circuit1 C1 (.x(sw),.z(led[0])); //instantiate the x and z to switches and LED
endmodule
Go to Digilent Nexys 4 webpage and download the xdc zip file
http://www.digilentinc.com/Data/Products/NEXYS4/Ne...
Save under a directory that you can have access to and unzip it
Under the project manager panel. Double click "Add Source". Choose "Add or Create Constraint".Click Next
Click Add file. Choose the "Nexys4_Master.xdc" . Click Finish
Expand the Constraint folder under sources panel and double click the xdc file
Uncomment the SW 0 to 3 by deleting the "#". The bold parts should not have any "#" at the beginning
Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0
set_property PACKAGE_PIN U9 [get_ports {sw[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] Bank = 34, Pin name = IO_25_34, Sch name = SW1 set_property PACKAGE_PIN U8 [get_ports {sw[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2 set_property PACKAGE_PIN R7 [get_ports {sw[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3 set_property PACKAGE_PIN R6 [get_ports {sw[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
Uncomment the led 0 by deleting the "#". The bold part should not have any "#" at the beginning
Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0
set_property PACKAGE_PIN T8 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
Double click "Run Synthesis" under the project manager panel . Vivado will ask you to save all changes you made before the synthesis. Click OK to save all changes to start the synthesis. Once it is successfully completed, the implementation pop up. Choose implementation and Click OK.
Double click generate bitstream file and generate the bitstream file
Expand the Hardware Manager and then double click the target hardware. A wizard pops up. Click Next
Choose connect to local server (machine)
Grab the Digilent Nexys 4 and connect it to the USB port of the computer. Turn on the Nexys 4. There is a test demo showing up (LED is blinking and Seven Segment Display is showing 1 to 5). Click Next.
Vivado will detect the Nexys 4 automatically. Click Next --> Next to open the hardware
So only SW0, SW1, SW2 and SW3 all switch on, then LD0 will be on.
The upper picture shows all switches are off, so LED is off. The bottom one shows all are on, so the LED (LD0) is on
The project file has been attached.